The performance of many photonic circuits is often highly sensitive to temperature variations and thermal crosstalk between devices. Many modern photonic integrated circuits (PICs) are fabricated using advanced lithography and etching techniques originally developed for CMOS processes on top of a traditional silicon handle wafer. An example of a traditional PIC 10 fabricated on a silicon-on-insulator (SOI) wafer is shown in FIG. 1 (not to scale). The PIC 10 is packaged on a printed circuit board (PCB)/package 12, which uses an electrically conductive pathway, such as a wirebond 14, to provide electrical communication between electronic circuitry in the PIC 10 and circuitry in the PCB/package 12. The silicon in an SOI wafer is etched to form SOI structures 18 on a buried oxide (BOX) layer 16 that was provided on a surface of the SOI wafer (e.g., an oxide material such as silicon dioxide). The SOI structures 18 may include waveguides or other structures along with structures etched from material deposited or grown in different layers (e.g., germanium, silicon nitride, and/or metals), for example, to form devices that may include photonic and/or electronic functionality. Various layers can be stacked in a combined structure, for example, using oxide 20 that is deposited at various stages between the formation of different layers. In some cases, instead of embedding structures in oxide, there may be free-standing structures to enable mechanical movement (e.g., for MEMS devices). Before those structures are formed, the BOX layer 16 is bonded to a stiff supporting substrate in the form of a silicon wafer, called a silicon handle 22, which provides mechanical stability for the fabrication process. However, the presence of the silicon handle 22 potentially degrades the high-speed performance of radio frequency (RF) photonics chips by creating loss and parasitic effects on transmission lines and can lower the efficiency of optical edge coupling. Moreover, the relatively high thermal conductivity of silicon (compared to silicon oxide and nitride films) reduces the thermal isolation of adjacent devices. Therefore, if the temperature of a photonics device is to be controlled (for example for tuning the refractive index through thermal control), more power may need to be consumed for such control, and also adjacent photonic devices may suffer from thermal crosstalk through the thin BOX layer 16 and the silicon handle 22.